How NAND Flash Cells Store Data
NAND flash memory stores data by trapping electrons in an insulated layer within each memory cell. Each cell is a field-effect transistor with an additional floating gate (or charge trap layer) that holds electrons even when power is removed. The number of electrons stored determines the cell's threshold voltage, which the controller reads to determine the stored bit value. A single NAND chip contains billions of these cells organized into pages and blocks.
Floating Gate and Charge Trap Architectures
Early NAND flash used floating gate cells: a conductive polysilicon layer electrically isolated by thin oxide layers above and below. Electrons tunnel through the oxide onto the floating gate during a program operation (applying a high voltage to the control gate). During an erase operation, a reverse voltage pulls electrons off the floating gate through the tunnel oxide.
Modern 3D NAND (V-NAND) uses charge trap flash (CTF) cells. Instead of a conductive floating gate, CTF cells use a silicon nitride insulating layer to trap electrons at discrete locations. The advantage is that a leak in the tunnel oxide does not drain the entire floating gate; trapped charges at individual sites are isolated from each other. This improves data retention in high-layer 3D stacks where the tunnel oxide is under more mechanical stress.
Both architectures store data the same way: the number of trapped electrons sets the cell's threshold voltage. The controller applies a reference voltage and checks whether current flows through the cell. If the threshold voltage is above the reference, the cell is in one state; if below, it is in another. Multiple bits per cell require multiple reference voltages to distinguish more states.
SLC, MLC, TLC, and QLC: Bits per Cell
- SLC (Single-Level Cell)
- 1 bit per cell, 2 voltage states. The controller only needs to distinguish "charged" from "not charged." Wide voltage margins make reads fast and reliable. Highest endurance but lowest density and highest cost per gigabyte.
- MLC (Multi-Level Cell)
- 2 bits per cell, 4 voltage states. The voltage window is divided into four bands. Tighter margins than SLC mean slower reads and more susceptibility to voltage drift from cell aging.
- TLC (Triple-Level Cell)
- 3 bits per cell, 8 voltage states. The dominant technology in consumer SSDs. The narrow voltage bands between states make TLC more sensitive to read disturb, charge leakage, and temperature fluctuations.
- QLC (Quad-Level Cell)
- 4 bits per cell, 16 voltage states. Maximum density, lowest cost. The voltage margins are so narrow that QLC cells require more aggressive ECC and have the lowest endurance ratings. Used in read-heavy or archival workloads.
| Cell Type | Bits/Cell | Voltage States | Typical Endurance (P/E Cycles) |
|---|---|---|---|
| SLC | 1 | 2 | 50,000 - 100,000 |
| MLC | 2 | 4 | 3,000 - 10,000 |
| TLC | 3 | 8 | 500 - 3,000 |
| QLC | 4 | 16 | 100 - 1,000 |
Program/Erase Cycles and Endurance Limits
Every program/erase (P/E) cycle damages the tunnel oxide slightly. Electrons tunneling through the oxide layer leave behind trapped charges (oxide traps) that gradually change the cell's electrical characteristics. After enough cycles, the oxide becomes leaky enough that the cell can no longer reliably hold its programmed charge for the required data retention period.
The controller tracks the P/E cycle count per block and uses wear leveling to distribute writes evenly across all blocks. When a block's cycle count approaches the rated endurance, the controller may retire it from the active pool and allocate a spare block. SMART attribute 177 (Wear Leveling Count) on many SSDs reports the remaining endurance as a percentage.
Read Disturb and Data Retention
Reading a NAND cell requires applying a voltage to the wordline (control gate). This read voltage, while lower than a program voltage, can still cause a small amount of electron tunneling into neighboring cells on the same page or block. After many read operations on the same block, the accumulated charge shift can flip bit values in cells that were not being read. This is called read disturb.
The controller mitigates read disturb by tracking read counts per block and performing background refresh operations: reading the block's data, erasing the block, and reprogramming the data. If the controller fails (power loss, firmware crash), read disturb errors accumulate unchecked.
Data retention refers to how long a programmed cell can hold its charge without power. At room temperature, a new TLC cell retains data for years. A worn TLC cell near its endurance limit may retain data for only weeks or months. High temperatures accelerate charge leakage. This is why SSDs left unpowered for extended periods, particularly worn SSDs, may develop uncorrectable errors when powered back on.
Data retention degrades with cell wear and temperature.
A heavily worn TLC SSD stored unpowered in a hot environment (above 40°C) may lose data in a matter of months. JEDEC standards specify data retention of 1 year at 30°C for client SSDs at end-of-life endurance. Enterprise SSDs have tighter retention specifications.
Frequently Asked Questions
What is the difference between SLC, MLC, TLC, and QLC?
SLC stores 1 bit per cell (2 voltage states), MLC stores 2 bits (4 states), TLC stores 3 bits (8 states), and QLC stores 4 bits (16 states). More bits per cell means higher density and lower cost, but also lower endurance and slower writes because the controller must place the charge more precisely among more voltage levels.
Can data be recovered from worn-out NAND cells?
When cells wear beyond their rated endurance, they lose charge retention and develop bit errors. If errors exceed the ECC correction capability, the controller marks blocks as bad. Data written before the cells degraded may still be readable if ECC or recovery tools can correct the accumulated errors. Data written at the end of cell life, when error rates are highest, may be unrecoverable.
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