Is Your NVMe Drive Dead?
An NVMe drive that vanishes from BIOS or reports 0 bytes is almost always suffering from firmware panic or PCIe link failure, not dead NAND. Consumer recovery software cannot access a controller that never completed PCIe enumeration. Power the drive off and do not run chkdsk or disk utilities.
- ●Drive not detected in BIOS/UEFI at all
- ●Windows Disk Management shows 0GB, 2MB, or 20MB capacity
- ●Device Manager shows a controller alias like SM2263XT or SATAFIRM S11 instead of the drive model name
- ●"Inaccessible Boot Device" BSOD on a previously working system
- ●Drive enumerates in BIOS but hangs or times out when accessed
Software like Disk Drill, EaseUS, or chkdsk operates through the OS storage driver stack. If the controller is panicked, the OS never sees a valid block device. Running chkdsk on a degraded NVMe drive forces read retries that stress marginal NAND cells and can trigger TRIM operations that permanently erase recoverable data. The only safe action is to power the drive off and send it for professional evaluation.
NVMe PCIe Architecture and Failure Points
NVMe drives connect directly to the CPU via PCIe lanes, bypassing the SATA host bus adapter. This eliminates latency but introduces new failure modes: link-training stalls in Detect or Polling states, reference clock loss, and firmware corruption that passes link training yet fails NVMe initialization.
The PCIe Link Training and Status State Machine moves through a fixed sequence on every cold boot. Each stall location maps to a specific physical fault that determines whether recovery starts with board repair or firmware reconstruction.
- Detect.Quiet / Detect.Active
- The host never sees receiver termination. The drive's PCIe PHY is not powered or its bond wires are open. The cycle repeats at roughly 12 ms intervals indefinitely. Cause: PMIC failure, controller power-rail collapse, or a destroyed PHY analog block. Recovery path: board-level repair first.
- Polling
- Receiver detected but the drive cannot lock onto the host clock or achieve symbol-lock on TS1/TS2 ordered sets. Cause: damaged PCIe lanes, cracked solder under the controller BGA, or a degraded reference clock crystal. Recovery path: PC-3000 forces stable Gen1 connection to bypass the lock failure.
- Configuration
- Bit-lock achieved at Gen1 (2.5 GT/s) but the link cannot negotiate full width or speed. The drive enumerates at x1 Gen1 instead of x4 Gen4. PC-3000 forces a stable Gen1 connection for imaging instead of letting the host retry at higher speeds.
- Recovery.Equalization
- Common stall point on Gen4 and Gen5 drives. Equalization tuning at 16 GT/s or 32 GT/s fails because the controller silicon has thermally degraded or the M.2 edge connector contacts are oxidized. Forcing the link down to Gen3 or Gen2 usually clears it long enough to image.
- L0 reached
- The physical link is healthy. Whatever is wrong with the drive lives above the PHY layer. Recovery shifts to firmware diagnostics: Identify Controller, Get Log Page SMART/Health, and namespace verification.
DRAM vs. Host Memory Buffer: Where the FTL Lives
| Feature | DRAM-equipped NVMe | DRAMless HMB NVMe |
|---|---|---|
| FTL cache location | Onboard DDR4 DRAM chip | Borrowed from host system RAM via PCIe |
| Power loss behavior | FTL in onboard DRAM persists briefly; enterprise drives flush to NAND via capacitors | FTL in host RAM vanishes instantly when the system loses power |
| FTL corruption risk | Lower; periodic NAND checkpoints supplement DRAM copy | Higher; relies solely on periodic NAND checkpoints |
| Recovery complexity | FTL usually reconstructable from NAND checkpoints | FTL reconstruction may require scanning all NAND pages for metadata fragments |
| Common drives | Samsung 980 Pro/990 Pro, WD Black SN850X, Corsair MP600 | Samsung 980 (non-Pro), WD SN580, Kingston NV2, most budget NVMe |
DRAMless HMB drives trade FTL resilience for lower cost and power consumption. The trade-off becomes critical only during unplanned power loss. If you use a DRAMless NVMe drive for work that cannot be recreated, a UPS is the single most effective protection against this failure class.
LTSSM Deep Dive: Why NVMe Drives Vanish from BIOS
Most "no NVMe device found" failures map to one of three regions of the PCIe Link Training and Status State Machine: a Detect or Polling stall (no electrical link), a Recovery.Equalization stall at Gen3/Gen4/Gen5 (link forms then collapses under speed step-up), or an L0-reached firmware panic (link is healthy, the controller never answers Identify Controller). The diagnostic question is which region. PC-3000 Portable III reads the answer from PCIe Configuration Space.
The LTSSM is a gate-level logic block in the PCIe MAC layer that exchanges TS1 and TS2 Ordered Sets at 2.5 GT/s to establish bit-lock, symbol-lock, lane numbering, and link width before any NVMe command is sent. It runs on every cold boot and on every wake from L1.2 or L2 sleep. A drive that fails to reach L0 has a physical-layer or PHY fault. A drive that reaches L0 and then drops to Recovery in a loop has a signal integrity or thermal fault. A drive that reaches L0 and stays there but never completes NVMe initialization has a controller firmware or FTL fault. These three regions require three different lab interventions.
Full LTSSM State Reference
- Detect (Detect.Quiet, Detect.Active)
- Entry state after PERST# or power-on. The host transmitter tests for receiver termination on each lane. If no termination is seen, the state machine loops back to Detect.Quiet every 12 ms indefinitely. Cause when stalled: dead PMIC, shorted voltage regulator on the PCB, open bond wires on the controller, or destroyed PHY analog block. Board repair first.
- Polling (Active, Configuration, Compliance)
- Link partners exchange TS1 then TS2 at 2.5 GT/s to achieve bit-lock and symbol-lock. Polling.Compliance is a substate entered when a passive test load is detected instead of a live partner. Cause when stalled: cracked BGA solder on a differential pair, oxidized M.2 contacts, severe impedance mismatch from a cheap adapter, or a degraded reference clock crystal.
- Configuration
- Lane numbering and link-width negotiation. Both ends send TS1 and TS2 with lane and link numbers, and lane reversal is resolved here. Cause when stalled: severed differential pairs that force a width fallback the controller cannot accept, or firmware that refuses the negotiated configuration.
- L0 (Active Data State)
- Transaction Layer Packets and Data Link Layer Packets flow. The physical link is healthy. Reaching L0 at Gen1 is a prerequisite for stepping up to Gen3, Gen4, or Gen5 through Recovery. If the drive sits at L0 but the host reports no device, the problem is above the PHY: NVMe Identify Controller is timing out or returning a generic alias.
- L0s, L1, L1.1, L1.2, L2 (power management)
- L0s is a low-latency electrical-idle. L1 is a deeper save where the reference clock may be gated by CLKREQ#. L1.1 and L1.2 disable internal PLLs for longer wake latency. L2 is deep sleep with main power removed. Early Phison PS5012-E12 firmware has a documented L1.2 retrain bug where the PHY fails to come back from sleep, which surfaces as "drive disappears after hibernate" until a cold PERST# is forced.
- Recovery (RcvrLock, Speed, Equalization, RcvrCfg, Idle)
- Entered to change link bandwidth, change width, or re-establish a link that has accumulated bit errors in L0. Recovery.Equalization is where Gen3+ tuning happens across four phases. A drive that link-flaps between L0 and Recovery is the classic cracked-BGA signature: cold link works, thermal expansion opens a microfracture under load, link collapses, drive cools, link reforms.
- Loopback
- Diagnostic state for bit-error-rate verification. The master sends data the slave echoes back without passing it to higher protocol layers. Rarely entered on consumer drives outside of lab testing.
- Hot Reset
- In-band reset. The root complex transmits continuous TS1 Ordered Sets with the Hot Reset bit asserted, and the endpoint enters the Hot Reset state after receiving two consecutive TS1s with the bit set, then drops to Detect once the Hot Reset state times out. Triggered by the host when the NVMe Admin Queue times out or an Advanced Error Report fires. Windows logs this as Event ID 129 (Reset to device).
- Disabled
- The host directs the link into Disabled by sending TS1 with the Disable Link bit asserted, and the endpoint drives electrical idle. The drive becomes invisible to BIOS and Device Manager and will not retrain until a fundamental PERST# reset or full power cycle. BIOS sometimes parks a drive here during POST when the link causes fabric errors.
Equalization Phases 0 to 3 (Gen3 and Above)
At Gen3 (8 GT/s), Gen4 (16 GT/s), and Gen5 (32 GT/s), channel insertion loss and inter-symbol interference make raw signaling unreliable. The Recovery.Equalization substate tunes the transmitter Finite Impulse Response presets and the receiver Continuous Time Linear Equalization and Decision Feedback Equalization across four phases. Each phase has a tight timeout. If the link cannot reach the required Bit Error Rate within roughly 24 ms, the LTSSM downgrades speed and restarts.
- Phase 0
- Still at 2.5 GT/s. The host sends initial TxEQ preset values (Preset 0 through 10) to the drive via TS2 ordered sets. The drive prepares to apply them on speed step-up. A Phase 0 stall usually means a receiver-side logic fault inside the controller.
- Phase 1
- Speed steps up to the target rate. Both ends exchange TS1 with the negotiated presets and must achieve a Bit Error Rate of 10^-4 or better to advance to Phase 2. Symbol-lock itself was established earlier during Polling. Phison E18 drives in the Kingston KC3000 family commonly fail Phase 1 at Gen4 because thermal cycling has cracked the BGA solder on a differential pair, raising channel loss past what CTLE can compensate. The LTSSM downgrades to Gen3 or Gen1 and retries.
- Phase 2
- The host fine-tunes the drive's transmitter by requesting specific preset or cursor changes. The drive applies them and reports back. Optimizes the eye diagram for the host's receiver.
- Phase 3
- Roles reverse. The drive requests TxEQ coefficient changes from the host to optimize the drive's own receiver. A Phase 3 stall means the controller's internal equalization logic could not process the host's coefficient updates, forcing a speed downgrade or link drop. Common on Crucial T700 and Corsair MP700 (Phison PS5026-E26) when thermal degradation has shifted the SerDes switching thresholds.
Lane-Width Negotiation and x4 to x1 Fallback
A standard M.2 NVMe drive runs at x4. During Configuration, the root complex verifies receiver termination on each lane. If a differential pair is severed (bent M.2 pins, BGA microfractures, lifted PCB pad), the LTSSM drops the dead lanes and brings the link up at x2 or x1. Speed degradation works the same way: failed equalization at Gen4 forces fallback to Gen3, then Gen2, then Gen1.
The fallback is observable in PCIe Configuration Space. The Link Capabilities Register at offset 0Ch reports the maximum hardware width and speed. The Link Status Register at offset 12h reports the currently negotiated width and speed. A mismatch (Max Width x4, Negotiated Width x1) is direct evidence of physical-layer damage on at least one lane.
| Config Space Field | Healthy Gen4 x4 | Degraded |
|---|---|---|
| Current Link Speed (offset 12h, bits 3:0) | 0100b = 16 GT/s | 0001b = 2.5 GT/s |
| Negotiated Link Width (offset 12h, bits 9:4) | 000100b = x4 | 000001b = x1 |
| Link Training bit | 0b (complete) | 1b (stalled in Config or Recovery) |
Differential Diagnosis: LTSSM Stall vs. Controller Firmware Panic
The same surface symptom ("NVMe not detected in BIOS") maps to two opposite root causes. Recovery for an LTSSM stall starts with board-level repair to revive the PHY. Recovery for a firmware panic starts with PC-3000 ROM-mode entry and FTL reconstruction. The detailed firmware-side workflow is covered on our firmware panics and ROM mode page. The flagship NVMe data recovery page covers the broader service.
| Symptom | LTSSM-side cause | Controller/NAND-side cause | First PC-3000 Portable III diagnostic |
|---|---|---|---|
| Drive absent from BIOS, no enumeration | LTSSM stuck in Detect.Quiet; PMIC dead or PHY destroyed | Not the cause: a controller firmware fault cannot prevent Detect from completing | Diode-mode short check on 3.3V rail; FLIR scan for hotspot before any power-up |
| Drive enumerates intermittently, drops under load | Link-flap between L0 and Recovery; cracked BGA solder opens when hot | Rare; firmware thermal throttling on Phison E26 can also drop the link, but gracefully | Force Gen1 x1 in PC-3000 PCIe init; read Link Status Register offset 12h while heating the controller |
| Drive enumerates at x1 Gen1 instead of x4 Gen4 | Severed differential pair; bent M.2 pin; oxidized contact | Not the cause: firmware does not control negotiated width | Read Link Capabilities offset 0Ch vs. Link Status offset 12h to confirm width mismatch |
| Drive shows up as "SATAFIRM S11", "SM2263XT", or "Phison PS5012" with 0 GB capacity | Not the cause: LTSSM reached L0 successfully; this is past the PHY layer | Controller in ROM mode after firmware panic; FTL or service area corrupted beyond self-repair | Confirm L0 via Configuration Space, then short ROM_CS pad and inject SRAM loader |
| BIOS POST hangs for 30+ seconds, then drive marked absent | Possible Recovery.Equalization timeout loop at Gen4 or Gen5 | L0 reached but NVMe Identify Controller (Opcode 06h) times out; common on Samsung Elpis and Pascal | Pin link to Gen1 x1; if Identify still times out, the fault is firmware-side and not PHY-side |
| Drive vanishes only after hibernate or sleep | L1.2 wake retrain failure (early Phison E12 firmware) or REFCLK gated incorrectly | Less common, but firmware that fails to checkpoint FTL before sleep can panic on wake | Force cold PERST# from PC-3000; if link returns, fault is in L1.2 retrain path |
The diagnostic order matters. If a drive never reaches L0, no amount of firmware work helps because there is no logical channel to send commands. If a drive reaches L0 cleanly and stays there, board repair is wasted effort because the hardware is fine. PC-3000 Portable III gives both reads (Configuration Space and Identify Controller response) within the first few seconds of a bench session, which sets the recovery tier on the quote before any paid work begins. Cases that need board repair before firmware work fall in the $600–$900 circuit board tier plus the $900–$1,200 firmware tier.
The PC-3000 Portable III NVMe Recovery Workflow
The PC-3000 Portable III with the PCIe NVMe adapter on Port 0 acts as its own Root Complex, bypassing the host BIOS and OS. The workflow moves from electrical diagnosis to pin-shorting Techno Mode entry, SRAM loader injection, Virtual Translator construction, and sector-by-sector data extraction.
- 01
Pre-power electrical diagnostics
The M.2 PCB is inspected with a multimeter in diode mode before any power is applied. A shorted 3.3V rail to ground indicates a blown PMIC or shorted multilayer ceramic capacitor. FLIR thermal imaging localizes the heat signature. Powering a shorted drive forces current through the fault and risks destroying the controller die. Board-level repair must happen before any logical recovery is attempted.
- 02
Techno Mode entry via pin shorting
The controller boot sequence starts from an internal Mask ROM before loading firmware from NAND. By shorting the diagnostic test point (such as ROM_CS or UART_TX pads) to ground during power-on, the BootROM halts in a minimal diagnostic state. This bypasses the corrupted firmware loop and exposes the controller to PC-3000. The specific test point varies by controller family; PC-3000 documentation identifies the correct pad for each supported silicon revision.
- 03
SRAM loader injection
PC-3000 connects via the M.2 NVMe adapter on Port 0 and detects the ROM-mode controller. It sends a vendor-specific volatile microcode loader (LDR) directly into the controller's on-die SRAM. The loader is specific to the controller silicon revision, NAND chip ID, and firmware version. It executes from SRAM without writing to NAND, disabling wear leveling, garbage collection, and TRIM during imaging.
- 04
Virtual Translator construction
The loader provides raw NAND access. PC-3000 scans physical NAND pages and reads the Out-of-Band spare-area metadata: LBA stamps and chronological sequence numbers. A virtual Logical-to-Physical (L2P) table is built in workstation RAM. Where multiple physical pages claim the same LBA, the utility picks the one with the highest sequence number. This reconstructs the FTL mapping without writing anything back to the patient drive.
- 05
Targeted data extraction
PC-3000 Data Extractor issues logical reads against the virtual translator and routes them as physical-page fetches through the LDR. The entire drive is imaged sector-by-sector to a known-good destination before the drive is powered down. Files are verified against directory structure and transferred to your return media.
The PC-3000 Portable III hardware acts as a PCIe Root Complex, managing memory mapping and doorbell signaling to communicate with NVMe controllers that have entered a fault state. It supports vendor-specific diagnostic modes for select Phison, Silicon Motion, and Marvell NVMe controllers. Each controller family requires its own utility module, loader payload, and FTL reconstruction algorithm. Using the wrong module renders the recovery attempt useless.
Why Chip-Off Fails on Modern NVMe SSDs
Modern NVMe controllers implement AES-256 encryption with the media encryption key generated on the controller and wrapped by a key tied to a hardware-unique root in the controller's one-time programmable (OTP) memory. The key never leaves the controller die. Removing NAND chips for chip-off produces only ciphertext that cannot be decrypted without the original silicon.
Phison PS5012-E12, PS5016-E16, and PS5021-E21 controllers implement hardware AES-256 encryption. Silicon Motion SM2262EN and SM2269XT families also bind encryption keys to controller fuses. The NAND contents are encrypted at the hardware level before being written to flash. If the controller is electrically dead, chip-off yields only ciphertext. There is no offline path to decrypt it.
Board repair is not a separate service from data recovery on encrypted NVMe drives; it is the recovery path. We locate the failed component using FLIR thermal imaging, replace the shorted PMIC or voltage regulator with a Hakko FM-2032 on an FM-203 base station, and bring the original controller back to life. When the controller boots, the encryption keys are intact and your data is accessible. Board repair IS data recovery for encrypted NVMe drives.
Chip-off remains a viable fallback only on non-encrypted drives with destroyed controllers, where the NAND holds plaintext. PC-3000 Flash reads raw NAND pages and reconstructs the FTL mapping table. For encrypted drives, this produces unreadable data. We determine encryption status during the free evaluation and inform you before any paid work begins.
Controller-Specific NVMe Recovery Notes
Each NVMe controller family requires a different PC-3000 utility module, diagnostic mode entry sequence, and FTL reconstruction algorithm. ACELab PC-3000 SSD v3.8.10 supports Phison, Silicon Motion, and Marvell NVMe controllers directly.
Phison E12 / E16 / E21
Phison PS5012-E12 (Gen3), PS5016-E16 (Gen4), and PS5021-E21 (Gen4) controllers enter ROM mode when the NAND-resident firmware fails validation. PC-3000 detects ROM mode and injects the matching Phison loader into SRAM. Early E12 firmware has a documented L1.2 power-state re-initialization bug: the PHY fails to retrain after sleep or hibernate. PC-3000 forces a cold PERST# reset to restore link training. The PS5016-E16 runs hotter than later Gen4 designs and is prone to thermal FTL corruption. Recovery requires the PC-3000 Portable III with the Phison Active Utility.
Silicon Motion SM2262EN / SM2263XT / SM2267XT / SM2269XT
Silicon Motion NVMe controllers use a NANDXtend ECC engine. When the FTL collapses, the drive enumerates but advertises an anomalous capacity (0 GB, 1 GB, or 1023 MB) and surfaces the generic controller string instead of the OEM model name. Recovery follows the ROM-mode workflow: short the diagnostic test point on the PCB, inject the volatile loader into SRAM, and rebuild the translator from OOB spare-area metadata. The SM2267XT in the Kingston NV2 and the SM2269XT in newer budget Gen4 drives both follow this same safe-mode and microcode injection workflow.
Marvell 88SS1320
The Marvell 88SS1320 series is a PCIe Gen4 NVMe 1.4 design with a triple-core ARM Cortex-R5 processor and a four-channel NAND interface at 1200 MT/s. It is rare in consumer intake and shows up predominantly in OEM designs. Recovery is limited to board-level repair to preserve the original controller. Because the 88SS1320 is currently absent from the ACELab PC-3000 SSD supported list, firmware-level FTL reconstruction or SRAM loader injection is not possible if the controller itself has panicked.
Samsung Phoenix / Elpis / Pascal
Samsung's in-house controllers run the 970 EVO/Pro (Phoenix), 980 Pro (Elpis), and 990 Pro (Pascal) product lines. These controllers implement always-on AES-256 encryption with keys stored in the controller's secure area. Rossmann does not currently offer in-lab recovery for modern Samsung in-house controllers such as Phoenix, Elpis, or Pascal. Board-level repair to preserve the original controller is the only potential path, but full FTL reconstruction through PC-3000 is not available for these families.
Realtek
Realtek RTS5762 and RTS5763DL controllers are absent from the ACELab PC-3000 SSD supported list. Rossmann does not currently offer in-lab recovery for Realtek controllers. Realtek implements proprietary XOR data scrambling tied to the controller's internal key material. Chip-off without the original Realtek silicon yields pseudo-random noise, not usable data.
Innogrit
Innogrit controllers are absent from the ACELab PC-3000 SSD supported list. Rossmann does not currently offer in-lab recovery for Innogrit controllers.
Maxio MAP1602 / MAP1602A
The Maxio MAP1602/MAP1602A is a 4-channel DRAMless controller common in 2024-2025 budget NVMe SSDs. It is explicitly absent from ACELab PC-3000 SSD v3.8.10. Rossmann does not currently offer in-lab recovery for Maxio MAP1602.
NVMe Data Recovery Pricing
NVMe recovery ranges from $200–$2,500 depending on the failure type. Every case starts with a free evaluation and a firm quote before any paid work. If we recover nothing, you pay nothing. No attempt fees. +$100 rush fee to move to the front of the queue.
| Tier | When It Applies | Price |
|---|---|---|
| Simple Copy | Your NVMe drive works, you just need the data moved off it | $200 |
| File System Recovery | Your NVMe drive isn't showing up, but it's not physically damaged | From $250 |
| Circuit Board Repair | Your NVMe drive won't power on or has shorted components | $600–$900 |
| Firmware Recovery | Your NVMe drive is detected but shows the wrong name, wrong size, or no data | $900–$1,200 |
| PCB / NAND Swap | Your NVMe drive's circuit board is severely damaged and requires NAND chip transplant to a donor PCB | $1,200–$2,500 |
A donor drive is a matching SSD used for its circuit board. Typical donor cost: $40–$100 for common models, $150–$300 for discontinued or rare controllers.
NVMe firmware recovery runs $900–$1,200. Cases requiring board-level repair to revive the controller before firmware work fall in the $600–$900 circuit board tier plus the firmware tier. Large labs typically quote $1,600 to $2,100 for NVMe firmware work. We publish our pricing because you should know what you are paying before you ship anything.
Frequently Asked Questions
Why is my M.2 NVMe SSD not detected in BIOS?
The drive either failed PCIe link training or the controller firmware panicked before completing NVMe initialization. Link training stalls happen when the PHY cannot lock onto the reference clock or negotiate lane width. Firmware panics happen when the Flash Translation Layer corrupts and the controller drops to ROM mode. Both prevent the BIOS from seeing a valid NVMe device. Consumer recovery software cannot fix either problem because the OS storage stack never sees the drive. Recovery requires the PC-3000 Portable III to act as an independent PCIe Root Complex and force communication with the controller. NVMe recovery starts at $200.
Does running CHKDSK on a corrupted SSD destroy data?
Yes, if the controller is already in a degraded state. CHKDSK issues read and write commands through the OS driver. A panicked controller may misinterpret those commands, trigger TRIM on still-recoverable blocks, or overwrite surviving FTL metadata. Each power cycle and access attempt stresses marginal NAND cells. If your NVMe drive shows 0 bytes, the wrong capacity, or is not detected in BIOS, power it off and do not run any software utility.
Can data be recovered from a dead NVMe SSD after a power surge?
Yes, if the NAND is intact and the controller can be revived. A power surge typically destroys the PMIC or a voltage regulator on the PCB, not the controller die itself. FLIR thermal imaging locates the shorted component. The Hakko FM-2032 replaces the failed part while the controller remains soldered in place, preserving the AES-256 encryption keys inside the silicon. Once power delivery is restored, PC-3000 Portable III forces link training and accesses the NAND through the revived controller. Cases requiring board repair before firmware work fall in the $600–$900 circuit board tier plus the firmware tier.
What does PCIe link training failure mean?
PCIe link training is the electrical handshake between the host and the NVMe drive. The Link Training and Status State Machine moves through Detect, Polling, Configuration, Recovery, and L0. A failure means the drive never reached L0, so no NVMe commands can be sent. Common causes include a lost 100 MHz REFCLK, cracked BGA solder joints under the controller, or a degraded PCIe PHY from thermal cycling. PC-3000 Portable III bypasses the host's link training and forces negotiation at Gen1 or Gen2 speeds to establish a stable connection.
Why does my NVMe drive say no device found?
That message means the host completed PCIe enumeration without finding a valid endpoint at the M.2 slot, or the endpoint timed out before responding to the NVMe Identify Controller command. The Link Training and Status State Machine either stalled in Detect, Polling, or Configuration (no electrical link), or reached L0 and then dropped during Recovery.Equalization at Gen3/Gen4/Gen5 speeds. A third possibility is that the link reached L0 but the controller never answered Opcode 06h within the BIOS timeout window, which usually points to firmware panic, not link failure. The PC-3000 Portable III reads the Link Status Register at PCIe Configuration Space offset 12h to see the negotiated width and speed, then forces a stable Gen1 x1 connection to bypass equalization stalls during imaging. $200 for simple copy, $900–$1,200 for firmware-side cases.
Why does my NVMe SSD not show up in BIOS even though it has a power LED?
Power LEDs on M.2 adapters or carrier boards only confirm that 3.3V is reaching the board, not that the controller has booted or completed link training. The PCIe LTSSM still has to walk through Detect, Polling, Configuration, and Recovery before the BIOS can enumerate the drive. A drive that has power but never appears in BIOS is usually stuck in Detect.Quiet (no receiver termination, often a dead PHY or cracked BGA), Polling.Active (cannot achieve bit-lock on TS1/TS2 ordered sets), or oscillating through Recovery (cracked solder joints that open when the controller heats up). PC-3000 Portable III pins the link to Gen1 x1 and reads Configuration Space directly, which often reveals the stall point even when the host BIOS gives up after the standard timeout.
Can an NVMe SSD be repaired to working condition?
Data recovery and functional repair are different goals. We recover your data by reviving the controller long enough to image the NAND contents. Full functional repair of a consumer NVMe SSD is usually not economical; the goal is extraction, not returning the drive to daily use. After recovery, we recommend replacing the drive with a new unit. Our focus is getting your files back, not fixing the hardware for reuse.
What is ROM Mode on an NVMe SSD?
ROM Mode is a minimal bootstrap state where the controller boots from its internal Mask ROM instead of the NAND-resident firmware. It happens when the firmware service area is corrupted beyond the controller's self-repair capability. In ROM Mode, the drive responds to a limited command set and reports a generic controller alias with 0 bytes capacity. PC-3000 detects ROM Mode and injects a volatile loader into controller SRAM to bypass the corrupted firmware and access the NAND directly.
How does TRIM affect deleted file recovery on NVMe?
TRIM makes deleted file recovery impossible on modern NVMe SSDs once garbage collection executes. The operating system sends Dataset Management Deallocate commands to the controller, which marks logical blocks as invalid. The controller's background garbage collector then physically erases those NAND blocks. After a physical erase, the data is gone at the transistor level. No software and no lab can reverse a hardware-level erase. Recovery of deleted files is only possible if TRIM did not execute: the drive was pulled immediately after deletion, TRIM was disabled, or the file system does not support TRIM.
What is the difference between firmware corruption and NAND degradation?
Firmware corruption damages the Flash Translation Layer, bad-block tables, or service-area code while the NAND cells themselves still hold readable charge. PC-3000 can rebuild the translator in workstation RAM and extract user data. NAND degradation is physical cell wear-out: oxide layer breakdown, raised uncorrectable error rates, and unreliable reads from the silicon itself. A firmware fault is logically reversible. Cell-level wear is not, though chip-off into PC-3000 Flash can sometimes salvage what remains on unencrypted drives.
How much does NVMe firmware recovery cost?
NVMe firmware recovery costs $900–$1,200. Cases that also need board-level repair to revive the controller before firmware work fall in the $600–$900 circuit board tier plus the firmware tier. Every case starts with a free evaluation and a firm quote before any paid work begins. If we recover nothing, you pay nothing. +$100 rush fee to move to the front of the queue.
NVMe SSD not responding?
Free evaluation. From $200. No data, no fee.