If your NVMe drive disappeared and matters, stop power-cycling it to see if it comes back. If the controller is partly alive but the host link is broken, repeated power-ups risk the controller completing queued TRIM or UNMAP (Deallocate) commands, and background garbage collection can then erase those NAND cells. Don't run recovery software either; a drive that fails PCIe enumeration is invisible to the operating system, so there is nothing for software to scan. Call (512) 212-9111 for a free evaluation.
Why Is My NVMe Drive Not Detected?
There is a difference worth pinning down first. A drive missing only from Windows Disk Management but present in BIOS is usually a logical problem: a dropped partition or a file system the operating system no longer mounts. A drive absent from BIOS entirely is physical: the controller never trained its PCIe link, so the firmware that BIOS talks to never woke up.
The first case sometimes responds to consumer recovery software. The second never does, because a controller that fails link training is electrically invisible to the host.
What Can You Check Before Sending the Drive In?
A few checks rule out the cheap problems. They take minutes and cost nothing, and they tell you whether the drive is genuinely dead or just misconfigured. Run them before assuming the worst.
- Reseat the M.2 drive. Power down, pull the drive, and reseat it firmly at the correct angle before securing the screw. A drive lifted off its contacts can drop from the bus entirely.
- Check the standoff. The mounting standoff has to sit under the right length hole (2280, 2260, 2242). A standoff under the wrong hole props the board up so the connector never seats, or flexes the PCB.
- Confirm slot keying and BIOS lane sharing. A SATA-keyed M.2 drive will not work in an NVMe-only slot, and some boards disable an M.2 slot when a specific SATA port or PCIe slot is populated. Check the manual.
- Test on a second motherboard. This is the decisive check. If the drive is absent from BIOS on two different boards, the problem is the drive, not the slot or the configuration.
If the drive is still absent from BIOS after all four checks, the controller has failed link training and a consumer fix is off the table. The next sections explain why software can't reach it and how the lab does.
How Much Does NVMe Recovery Cost?
The diagnosis is what separates this from a guess. We learn the LTSSM stall point and the controller's condition before quoting, so the price reflects the real work. Board repair covers the power tree and differential-pair faults that stop the link from training. A donor drive is a matching SSD used for its circuit board. Typical donor cost: $40–$100 for common models, $150–$300 for discontinued or rare controllers. No data recovered means no charge. +$100 rush fee to move to the front of the queue.
| Recovery Path | NVMe Price | Typical Timeline |
|---|---|---|
| Link stabilized at x1, board-level repair to hold it | $600–$900 | 3-6 weeks |
| Link trains but controller fails the NVMe handshake (system-area rebuild) | $900–$1,200 | 3-6 weeks |
| Controller destroyed, NAND transplant to donor PCB | $1,200–$2,500 | 4-8 weeks |
NAND transplant requires a 50% deposit and applies only when the controller die is gone. Donor drive cost is additional. SATA SSD board repair runs $450–$600 for comparison. All prices exclude tax & target drive. The board-repair side, fault by fault, lives on the PCIe lane fault repair page.
How Does the PC-3000 Portable III Talk to a Drive the Motherboard Can't See?
A normal motherboard slot tries to train the widest, fastest link the drive advertises: x4 at Gen4 on a modern NVMe SSD. A controller that is degraded but not dead frequently cannot sustain that. The negotiation collapses, the link never reaches a usable state, and the host gives up and shows nothing. From the user's seat the drive looks completely dead.
The lab approach inverts the motherboard's priorities. Instead of chasing the fastest link, the PC-3000 Portable III presents itself as a Root Complex that asks for the least: one lane, low speed. It caps negotiation at x1 lane width and steps the link speed down toward Gen1 if the higher generations will not stabilize.
The point is stability, not throughput. Imaging at x1 Gen1 is slow, but a slow link that holds is worth far more than a fast link that collapses. Once the controller answers on that single lane, the lab reads its identity, confirms the NAND is intact, and images sector by sector. The same drive that trains nothing in a motherboard slot becomes readable because the negotiation was forced down to what a sick controller can still manage.
What Is LTSSM and Where Does It Stall on a Failing NVMe Drive?
Before any NVMe command moves, the PCIe physical layer runs the Link Training and Status State Machine. LTSSM walks the link from electrical idle through a defined sequence (Detect, Polling, Configuration, L0) and falls back into Recovery when an established link goes unstable. On a failing drive the walk stalls at a specific state, and the stall point is the diagnosis. The flagship NVMe page covers the same sequence in its link-training section.
| LTSSM stall point | What it means | Diagnostic reading |
|---|---|---|
| Stuck in Detect | The link never sees a receiver on the far end of a lane | Severed TX or RX differential pair, dead PCIe PHY, or a controller with no power because the power tree collapsed |
| Stuck in Polling | Detect passed but the link cannot lock bit and symbol timing | Lost or noisy 100 MHz reference clock, or a degraded PHY that cannot hold timing |
| Stuck in Configuration | Timing locked but the ends cannot agree on lane width and polarity | One lane of a x4 link open, polarity inversion, or a partially severed pair; forcing x1 often gets past it |
| Recovery loops | The link reaches L0 then keeps falling back into Recovery | Unstable signaling, often a Gen3/Gen4 equalization failure; stepping the speed down to Gen1 at x1 stabilizes it |
| L0 reached, NVMe handshake fails | The link is trained but CC.EN never produces Controller Ready | The lanes are healthy; the controller firmware or system area is corrupt and needs rebuilding |
The reason this matters is that the repair changes with the stall point. A Detect or Polling stall is a hardware fault on the board: a rail, a clock, or a pair, addressed by microsoldering on the board-repair side. A Recovery loop is an instability that the Root Complex x1 approach often tames without an iron. A handshake failure after L0 is a firmware problem inside the controller, addressed by system-area reconstruction.
No software product reads or acts on the LTSSM. A drive stalled before L0 never presents a block device, so it is invisible to every consumer tool ever shipped. The Root Complex has to coax the link into a stable state first, and only the lab equipment can do that.
Why Can't Recovery Software Reach a Failed NVMe Controller?
Tools like R-Studio and DMDE are good at what they do: scanning a drive the operating system can see, rebuilding partition structures, carving files from a healthy block device. That is a real and useful job, and on a logically failed but physically healthy NVMe drive it is the right tool. It is not disparagement to say it cannot help here; it is the architecture.
The chain runs in one direction. The PCIe link has to train. The controller has to enumerate. The operating system has to build a block device. Only then can software open that device and read logical block addresses. Break the first link in that chain and every step after it is unreachable. A controller stalled in Polling, or stuck in a Recovery loop, never reaches the host root complex, so there is no device for software to open.
This is why the lab work happens below software entirely. The Root Complex forces a stable link where the motherboard could not, the controller enumerates on that forced link, and only then does imaging begin. Software operates on top of a working link; the lab's job is to build the link in the first place.
How Do Silicon Motion, Phison, and Marvell Drives Fail Link Training?
The three controller families that PC-3000 SSD images on NVMe (Silicon Motion, Phison, Marvell) share the same PCIe physical layer, so they fail in similar patterns. The Root Complex x1 approach applies to all three because it works at the link layer, below anything vendor-specific.
- Silicon Motion (SM2262EN, SM2263XT, SM2264)
- DRAM-less designs like the SM2263XT lean on a host memory buffer and run hot in cramped M.2 slots. Thermal stress degrades the PHY over time, so the drive that once trained x4 Gen3 starts stalling in Polling or looping in Recovery. Forcing x1 at a lower speed frequently brings it back long enough to image.
- Phison (E18 and peers)
- High-end Phison parts push Gen4 x4 and are sensitive to signal integrity at that speed. A marginal pair or a slightly degraded PHY shows up as a Gen4 equalization failure: the link reaches L0, then falls back into Recovery repeatedly. Stepping the negotiation down past the equalization point, to Gen1 x1, often stabilizes it.
- Marvell
- Marvell NVMe controllers turn up in OEM and enterprise drives. The same link-layer rules hold: a Detect stall points at a severed pair or a dead power rail, a Polling stall at a clock or PHY problem. The diagnosis follows the stall point, not the vendor name.
Coverage note: PC-3000 SSD NVMe imaging spans Silicon Motion, Phison, and Marvell. The link-diagnosis and Root Complex x1 work applies to any NVMe drive because it is link-layer electronics, but vendor-specific imaging afterward is what depends on the controller family. We confirm coverage at the free evaluation before quoting.
Can Chip-Off Skip a Dead NVMe Controller?
The marketing claim is appealing: pull the memory chips off the dead board, read them on a bench, skip the broken controller entirely. On older non-encrypted SSDs there is truth to it, and chip-off is a legitimate last resort when the controller die is destroyed.
On a modern hardware-encrypted NVMe drive it falls apart. The media-encryption key is generated inside the controller and wrapped by a key tied to that controller's hardware-unique root, so it never leaves the original silicon in plaintext. Desolder the NAND and the bytes come back as ciphertext. Bond them to a donor controller of the exact same part number and the donor still cannot unwrap the key, because its root is different.
That is the whole case for board and PCIe repair over chip-off on these drives. The only silicon that can decrypt the NAND is the original controller, so the recovery is to bring that controller back, force a stable link to it, and let it decrypt its own NAND through the normal translator. Even with encryption off, the controller's data scrambling and error-correcting code are still barriers a raw NAND read has to undo. The fuller breakdown is on the hardware encryption page, and the board-repair fault catalog is on the PCIe lane fault page.
Does NVMe Recovery Need a Cleanroom?
The cleanroom is the signature image of hard-drive recovery for a reason. A spinning platter is exposed to the air inside the drive, the head flies microns above it, and a single dust particle can crash the head. Opening that drive outside a particle-controlled environment risks the platter. That physics is real, and for hard drives it matters.
None of it applies to an NVMe SSD. There is nothing spinning and nothing flying. The NAND dies are bonded inside sealed BGA packages, the controller is a chip on a board, and the failure points are electronic: a power rail, a differential pair, a controller that will not train its link. You do not protect any of that with filtered air. You protect it from static, which is why the work happens at an ESD-safe bench.
So when a lab insists an NVMe drive needs a Class-100 laminar-flow cleanroom, it is either misapplying hard-drive procedure to solid-state media or using the cleanroom image to justify a higher bill. The honest description of NVMe recovery is microsoldering and link diagnosis. The longer version of why solid-state media does not need a cleanroom is on the SSD cleanroom myth page.
Why Should You Stop Power-Cycling a Dead NVMe Drive?
TRIM is a logical deallocate command, not an instant physical erase. The operating system tells the controller which blocks are no longer needed; the controller unmaps them from its translation table and returns zeros when those addresses are read, then garbage collection erases the physical cells afterward. On a drive that is failing on the host link, those queued operations can still run when power is reapplied, which is how a recoverable drive becomes an unrecoverable one.
Repeated power-ups also push current through whatever is degraded on the board, so each retry can spread the damage. The safe move on a dead NVMe drive is to stop, pull it, and bring it to a bench where the first power applied is current-limited and the link is coaxed up by a Root Complex rather than a motherboard chasing the fastest negotiation.
What Is the Lab Sequence for an Undetected NVMe Drive?
The sequence builds from cheapest test to most invasive, so nothing irreversible happens until the evidence calls for it. Every step runs on an ESD-safe bench with the drive off any production host.
- Logical-versus-physical confirmation. Establish whether the drive is absent from BIOS or only from the operating system. BIOS absence on a second board confirms a physical link-training failure rather than a logical fault.
- Root Complex enumeration at forced x1. Connect the drive to the PC-3000 Portable III acting as a Root Complex, cap negotiation at x1 lane width, and step the speed down toward Gen1. If the controller answers, read its identity and confirm the NAND geometry.
- LTSSM stall reading. If the link will not train even at x1, read where LTSSM stalls. Detect points at a severed pair or a dead rail; Polling at a lost clock or degraded PHY; a Recovery loop at an equalization instability.
- Power tree and signal check. Where the stall is hardware, verify the controller core rails and the differential pairs on the board-repair bench with Hakko FM-2032 microsoldering, Atten 862 hot air, and FLIR thermal localization, then retry enumeration.
- System-area check for handshake failures. If the link trains but the controller never asserts ready after CC.EN, the firmware or system area is corrupt; reconstruct it through PC-3000 SSD before imaging.
- Imaging through the original controller. With a stable link and a responding controller, image sector by sector, letting the original silicon decrypt its own NAND. Coverage spans Silicon Motion, Phison, and Marvell examples including the Phison E18 and the Silicon Motion SM2262EN, SM2263XT, and SM2264.
Frequently Asked Questions
Why is my NVMe drive not detected?
Can software recover a dead NVMe drive?
How does the PC-3000 Portable III talk to a drive the motherboard can't see?
What is LTSSM and why does where it stalls matter?
How long does NVMe PCIe diagnosis take?
What does a free NVMe evaluation cover?
Can chip-off read the NAND directly and skip a dead NVMe controller?
Do you need a cleanroom to recover an NVMe SSD?
Which NVMe controllers can you diagnose and image in-lab?
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