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SSD Garbage Collection and Data Loss

Garbage collection is the SSD controller's background process that physically erases NAND blocks marked as invalid by TRIM. Once GC completes an erase cycle, the data is permanently gone. Modern SSDs also enforce DZAT (Deterministic Read Zero After TRIM), which returns zeroes to any software that reads a TRIMmed address, even before GC finishes the physical erase. A free evaluation determines whether your data survived.

Louis Rossmann
Written by
Louis Rossmann
Founder & Chief Technician
Updated April 7, 2026

What Is SSD Garbage Collection?

SSD garbage collection (GC) is an automated background process run by the SSD's internal controller. It consolidates valid data from fragmented NAND blocks into clean blocks, then physically erases the old blocks so they can accept new writes. GC is the step that permanently destroys deleted data on an SSD.

When you delete a file, the operating system sends a TRIM command to the SSD. TRIM marks the file's logical addresses as invalid in the controller's Flash Translation Layer (FTL). TRIM does not erase anything. The controller queues those blocks for garbage collection, which runs during idle time and applies the erase voltage that resets the NAND cells to their unprogrammed state.

This two-step process is what makes SSD data recovery different from hard drive recovery. On a hard drive, deleted files stay on the magnetic platters until new data overwrites the same sectors. On an SSD, the controller actively hunts for stale blocks and erases them in the background, regardless of whether new data needs that space.

What Is DZAT (Deterministic Read Zero After TRIM)?

DZAT is a SATA specification feature where the SSD controller guarantees that any read request targeting a TRIMmed logical block address returns all zeroes. This happens immediately after TRIM processing, before garbage collection physically erases the NAND cells. The NVMe equivalent is DLFEAT=001b (Deallocate Logical Block Features).

DZAT (Deterministic Read Zero After TRIM)
The strictest SATA TRIM implementation. The controller intercepts all read commands to TRIMmed LBAs and returns a payload of all zeroes. The physical NAND may still hold the original charge states, but no software can reach them through the standard interface. Most modern SATA SSDs implement DZAT.
DRAT (Deterministic Read After TRIM)
A less strict implementation where the controller returns a consistent, deterministic value for TRIMmed LBAs. The value is usually zeroes but the specification allows other fixed patterns. Less common in modern drives.
DLFEAT=001b (NVMe Deallocate Features)
The NVMe equivalent of DZAT. When a drive sets DLFEAT to 001b in its namespace metadata, reading a deallocated logical block returns all zeroes. Most modern NVMe drives enforce this behavior for predictable latency and RAID parity consistency.

DZAT creates a critical problem for data recovery. The controller lies to the operating system. It reports that TRIMmed blocks contain nothing but zeroes, even while the original data still exists as electrical charges on the NAND cells. This is not a software limitation. It is a protocol-level enforcement built into the drive's firmware. The TRIM and DZAT protocol specifications define the exact ATA and NVMe opcodes, namespace metadata fields, and controller behavior that produce this zero-return result.

Why Does Recovery Software Fail on Modern SSDs?

Recovery software operates at the logical layer above the SSD controller. It sends standard read commands through the OS storage driver. When the controller has DZAT enabled, every read to a TRIMmed block returns zeroes. The software sees empty space and reports the data as unrecoverable.

LayerWhat HappensData Accessible?
File system (OS level)OS sends TRIM after file deletion; marks LBAs invalidNo; file metadata removed
Controller logical interfaceDZAT returns zeroes for all TRIMmed LBAsNo; software sees empty space
FTL mapping tableLBA-to-PBA mapping dropped; pages marked invalidNot through standard commands
Physical NAND cellsCharge states may still hold original data until GC erasesYes, via PC-3000 SSD raw NAND access

Tools like Disk Drill, EaseUS, Recuva, and R-Studio all operate at the top two layers. They cannot bypass the controller's DZAT enforcement, and they cannot access raw NAND pages below the FTL. When these tools report zero recoverable files from a TRIMmed SSD, the data may still exist physically on the NAND. It requires hardware that communicates with the controller at the diagnostic level, not through the standard storage protocol.

SSD Data Recovery Pricing

Five published tiers from From $200 to $1,200–$1,500. NVMe SSD recovery ranges from From $200 to $1,200–$2,500. Free evaluation, firm quote before any paid work. No data, no recovery fee. +$100 rush fee to move to the front of the queue.

Simple Copy

Low complexity

Your drive works, you just need the data moved off it

$200

3-5 business days

Functional drive; data transfer to new media

Rush available: +$100

File System Recovery

Low complexity

Your drive isn't showing up, but it's not physically damaged

From $250

2-4 weeks

File system corruption. Visible to recovery software but not to OS

Starting price; final depends on complexity

Circuit Board Repair

Medium complexity

Your drive won't power on or has shorted components

$450–$600

3-6 weeks

PCB issues: failed voltage regulators, dead PMICs, shorted capacitors

May require a donor drive (additional cost)

Firmware Recovery

Medium complexityMost Common

Your drive is detected but shows the wrong name, wrong size, or no data

$600–$900

3-6 weeks

Firmware corruption: ROM, modules, or system files corrupted

Price depends on extent of bad areas in NAND

PCB / NAND Swap

High complexity

Your drive's circuit board is severely damaged and requires NAND chip transplant to a donor PCB

$1,200–$1,500

4-8 weeks

NAND swap onto donor PCB. Precision microsoldering and BGA rework required

50% deposit required; donor drive cost additional

50% deposit required

Hardware Repair vs. Software Locks

Our "no data, no fee" policy applies to hardware recovery. We do not bill for unsuccessful physical repairs. If we replace a hard drive read/write head assembly or repair a liquid-damaged logic board to a bootable state, the hardware repair is complete and standard rates apply. If data remains inaccessible due to user-configured software locks, a forgotten passcode, or a remote wipe command, the physical repair is still billable. We cannot bypass user encryption or activation locks.

No data, no fee. Free evaluation and firm quote before any paid work. Full guarantee details. NAND swap requires a 50% deposit because donor parts are consumed in the attempt.

Rush fee: +$100 rush fee to move to the front of the queue.

Donor drives: A donor drive is a matching SSD used for its circuit board. Typical donor cost: $40–$100 for common models, $150–$300 for discontinued or rare controllers.

Target drive: The destination drive we copy recovered data onto. You can supply your own or we provide one at cost plus a small markup. All prices are plus applicable tax.

A donor drive is a matching SSD used for its circuit board. Typical donor cost: $40–$100 for common models, $150–$300 for discontinued or rare controllers.

ATA TRIM Protocol and the Recovery Window Inside Over-Provisioned NAND

The time between a file deletion and a successful PC-3000 SSD read depends on two things: what the host sent to the drive (the ATA or NVMe command payload) and what the controller decides to do with the over-provisioned NAND pool. Both layers are specified by JEDEC and the T13 ACS-4 standard, and both behave differently across controller families.

ATA DATA SET MANAGEMENT: the Command That Carries TRIM

TRIM is a feature of the DATA SET MANAGEMENT command (opcode 0x06), introduced in ACS-2 and refined in ACS-4. The host sets the Trim bit in the Count register, then transmits a buffer of LBA Range Entries. Each entry is an 8-byte structure: a 6-byte starting LBA followed by a 2-byte range length. Entries are packed into 512-byte sectors; a single command can carry up to 64 sectors, or 4,096 ranges per transfer. The controller queues those ranges into the FTL, walks the logical-to-physical map, and marks every matching page invalid. No NAND cell is touched by this command. The block-level ERASE that actually destroys the data is a separate, later step, run by garbage collection at the controller's discretion.

The NVMe equivalent is the Dataset Management command (opcode 09h) with the Deallocate attribute, defined in NVM Express 2.0. The namespace's DLFEAT field in Identify Namespace tells the host what the drive will return on a subsequent read to a deallocated LBA. DLFEAT bit values determine whether the drive guarantees zeros, guarantees a fixed deterministic value, or makes no guarantee at all.

Deterministic vs Non-Deterministic TRIM Return Behavior

Not every SSD enforces DZAT. The SATA spec allows three distinct behaviors for reads to TRIMmed LBAs, and an enterprise NVMe drive can advertise a fourth through DLFEAT. A drive that returns data non-deterministically can leak plaintext through the standard read path for a limited window; a drive that enforces DZAT cannot. Both states sit above the NAND itself; neither tells you whether the underlying cells have been physically erased.

Return ModeSpec SourceWhat a Read to a TRIMmed LBA Returns
Non-deterministicPre-ACS-2 (legacy)Implementation-defined. May return stale NAND contents, zeros, or different values on repeated reads.
DRAT (Deterministic Read After TRIM)ACS-2A consistent, fixed pattern on every read. Pattern is vendor-chosen but must not change across reads of the same LBA.
DZAT (Deterministic Read Zero After TRIM)ACS-2All zeros. Enforced by the controller on the read path, regardless of NAND state.
NVMe DLFEAT bits 2:0 = 001bNVM Express 2.0All zeros for deallocated logical blocks (the NVMe analogue of DZAT).
NVMe DLFEAT bits 2:0 = 000bNVM Express 2.0No guarantee. Reads may return any value. Present on some enterprise drives where Deallocate is a hint rather than a contract.

None of these modes describe what has happened at the NAND layer. They only describe what the controller returns on the host interface. PC-3000 SSD operates below this interface entirely, which is why DZAT enforcement does not block a lab recovery when the physical cells still hold charge.

How Over-Provisioning Preserves Invalidated Pages Across P/E Cycles

The recovery window is not a stopwatch. It is a count of program/erase cycles on other blocks between the moment TRIM ran and the moment wear-leveling scheduled the original block for erase. Over-provisioning is the reserve pool that gives the controller somewhere else to write while leaving invalidated pages in place.

Consumer SSDs typically allocate 7% of raw NAND to OP; mixed-workload enterprise drives allocate 20% to 28% (documented in JEDEC JESD218 and vendor datasheets). When OP is high, the controller has ample clean blocks to absorb host writes and can defer both GC and wear-leveling across thousands of write transactions. An invalidated page can survive until the controller's static wear-leveling sweep picks its block for refresh, which on lightly used drives happens once per thousands of P/E cycles on other blocks. This is why powering the drive off immediately halts the clock: with no host writes arriving, no OP pressure accumulates, no background sweep runs, and the invalidated pages stay programmed.

Conversely, a drive written near capacity operates with an OP that behaves like zero. Every new host write forces the controller to reclaim a block immediately. Under this pressure, foreground GC erases TRIMmed blocks within seconds, and the recovery window closes before the drive can be shipped.

PC-3000 SSD FTL Translator Snapshot Extraction

When a deletion event has already run but the NAND has not yet been erased, raw physical reads return the programmed cell states. They do not return files. A modern SSD scatters a single file across hundreds of physical pages on different dies, indexed only by the FTL translator. To turn raw NAND pages back into files, the lab must rebuild the translator as it existed before the deletion.

Controllers store copies of the FTL translator in the NAND service area as a power-loss recovery safeguard. Every time the translator updates, the controller commits a new generation to service-area logs and retires the oldest. The number of retained generations is controller-specific: Silicon Motion SM2259XT drives carry multi-generation translator backups in the service area; Phison E12 and E18 use a rolling journal; Samsung firmware commits a checkpointed translator on shutdown and between wear-leveling passes.

After PC-3000 SSD enters the controller's diagnostic mode, Data Extractor walks the service area, parses every retained translator generation, and presents them as rollback points. The engineer picks a generation dated before the deletion event. Data Extractor re-applies that translator on top of the raw NAND image; pages the current FTL marks invalid resolve against the older translator and reassemble as live files. The recovery is not a scan for file headers; it is a forensic rollback of the mapping table.

Two conditions determine whether this works. The target blocks must not have been erased by GC since the deletion (so the physical pages still hold data). The service-area translator log must contain at least one generation dated before the deletion event (so there is a rollback point to restore). Drives shipped powered off within hours of a deletion event typically satisfy both conditions.

How the SSD Controller Manages Garbage Collection

NAND flash cannot overwrite data in place. The SSD must erase an entire block (128 to 256 pages, typically 256KB to 4MB) before writing new data to any page within that block. Garbage collection exists to prepare erased blocks for future writes by reclaiming blocks that contain a mix of valid and invalid pages.

Page-Level Writes, Block-Level Erases

Pages (4KB to 16KB) are the smallest unit the controller can read or write. Blocks (groups of 128 to 256 pages) are the smallest unit the controller can erase. When the OS modifies a file, the controller writes updated data to a new, clean page and marks the old page as invalid in the FTL. This out-of-place write model means blocks gradually accumulate invalid pages alongside valid ones.

The GC Cycle

  1. Identification: The controller selects a block with a high ratio of invalid pages. Controllers track valid/invalid ratios for every block on the drive.
  2. Valid page migration: The controller reads the remaining valid pages from the target block and writes them to a clean, pre-erased block.
  3. Block erase: The controller applies erase voltage to the entire target block, resetting all cells (both previously valid and invalid) to the unprogrammed state (0xFF). This step permanently destroys the deleted data.

Background GC vs. Foreground GC

Background GC runs during idle periods without interrupting host I/O. The controller uses dedicated processing cores (Phison controllers use "CoX processors" for this) to clean blocks quietly. Foreground GC triggers when the pool of free blocks drops too low to handle incoming writes. The controller pauses host operations to erase blocks in real time, causing the latency spikes known as the "performance cliff." From a recovery perspective, foreground GC is the worst scenario: it erases TRIMmed blocks immediately to free space for new data.

Over-Provisioning and GC Timing

Over-provisioning (OP) is a reserve of NAND blocks hidden from the user. A drive with 10% OP always has a buffer of free blocks available for writes while background GC processes dirty blocks at its own pace. More OP means the controller can defer physical erasure for longer periods. A nearly full drive with minimal free space triggers aggressive foreground GC, erasing stale blocks within seconds of a TRIM command. Enterprise SSDs with 28% or more OP tend to have the most relaxed GC scheduling; consumer drives with 7% OP erase more aggressively.

Which Controllers Implement DZAT?

Every major SSD controller family implements DZAT or its NVMe equivalent (DLFEAT=001b). The differences that matter for data recovery are in GC timing: how quickly the controller physically erases TRIMmed blocks after the DZAT logical mask is in place.

Samsung Controllers (MKX, Elpis, Pascal)

Samsung designs controllers in-house: the MKX for the SATA 870 EVO, Elpis for the NVMe 980 PRO, and Pascal for the 990 PRO. Samsung firmware prioritizes aggressive GC for NAND endurance optimization. Background GC begins within seconds of idle time after receiving TRIM. Samsung's aggressive GC benefits drive longevity but creates the shortest recovery window of any controller family.

Phison Controllers (PS3111-S11, PS5012-E12, PS5018-E18)

Phison controllers power drives from Corsair, Kingston, Seagate, and Sabrent. Newer Gen4/Gen5 controllers (like the E18 and E26) use dedicated CoX processors for background GC, separating GC from host I/O processing. Older controllers like the PS3111-S11 have a documented firmware failure mode where GC operations cause the FTL to panic and throw the drive into SATAFIRM S11 safe mode. When this happens, GC freezes mid-cycle. The interrupted GC preserves NAND data that would otherwise have been erased, making PC-3000 recovery viable.

Silicon Motion Controllers (SM2258XT, SM2259XT, SM2262EN)

Silicon Motion controllers are used by Crucial, ADATA, and many OEM drives. The SM2259XT (a DRAM-less SATA controller) shows a favorable behavior for recovery: on a quick format, the controller erases the primary FTL translator but does not trigger a mass-GC cycle across the NAND array. The physical data persists on the memory cells. PC-3000 can access historical translator backups stored in the NAND service area and reconstruct the original directory structure. This makes Silicon Motion drives among the more recoverable after format events.

Marvell, Realtek, and Intel/Solidigm

Marvell controllers (enterprise-grade) follow strict DZAT compliance with steady, predictable GC timing. Realtek controllers appear in budget NVMe drives and can delay GC under heavy thermal throttling. Intel/Solidigm controllers enforce RZAT (Read Zero After TRIM) in enterprise environments where RAID parity consistency requires deterministic behavior across all drives in the array.

How Powering Off Preserves Data Before GC Completes

The gap between TRIM marking blocks as invalid and GC physically erasing those blocks is the only recovery window. Powering off the SSD immediately after data loss freezes the controller state and prevents GC from running.

  1. Power off the drive immediately. Disconnect the SSD from the system. Do not shut down the OS normally if you can avoid it; a normal shutdown gives the controller idle time to run GC before power is removed.
  2. Do not reconnect to a running OS. Plugging the SSD back into a running system sends queued TRIM commands and gives the controller idle time to resume GC. Even mounting the drive as read-only may trigger controller activity.
  3. Do not run recovery software. Consumer recovery tools send read commands through the standard interface. On a DZAT drive, these reads return zeroes (giving you no useful data). Worse, the drive is powered on and idle between read commands, allowing background GC to execute.
  4. Ship the drive powered off to a lab with PC-3000 SSD. The PC-3000 forces the controller into a diagnostic state that disables all background processes, including GC, before reading raw NAND.

If the SSD suffered a power loss or firmware failure before GC ran, the data is likely intact on the NAND. Firmware failures freeze the controller mid-operation, preventing all background tasks including GC. Drives stuck in safe mode (SATAFIRM S11, BSY state, 0-byte capacity) have not run GC since the failure occurred.

How PC-3000 SSD Reads Invalid NAND Pages

PC-3000 SSD bypasses the controller's standard SATA/NVMe interface entirely. Instead of asking the controller for logical data (which triggers DZAT zeroes), it communicates with the controller at the diagnostic level to access raw physical NAND pages that the FTL has marked as invalid but GC has not yet erased.

Safe Mode Entry and Loader Upload

The first step is preventing the controller from executing its standard firmware (and with it, background GC). Engineers use hardware techniques to force the controller into Safe Mode. With the primary firmware suspended, PC-3000 uploads a custom microcode loader directly into the controller's RAM. This loader grants access to Techno Mode.

Techno Mode: Freezing the Drive State

In Techno Mode, the SSD operates in a restricted, single-channel state. All background firmware tasks are disabled: no garbage collection, no wear leveling, no TRIM processing. The drive's forensic state is frozen. PC-3000 can now read raw Physical Block Addresses (PBAs) directly, bypassing the FTL mapping table and the DZAT logical mask.

FTL Translator Reconstruction

Raw NAND reads return fragmented data mixed with ECC parity bits and out-of-order blocks from wear leveling. To reconstruct usable files, the FTL translator must be rebuilt. Advanced SSD controllers (Silicon Motion SM2259XT, Phison E12) create backup copies of the FTL translator in the NAND service area as a safeguard against power loss. PC-3000 Data Extractor scans the raw NAND architecture for these historical translator backups, reverts the logical mapping to a version that existed before the deletion event, and rebuilds the original file system and directory structure.

This procedure depends on one condition: the physical NAND cells must still hold the original charge states. If GC has already erased the target blocks, the cells are reset to 0xFF and the data is gone. This is why immediate power-off is critical. For drives where the controller is dead beyond repair, chip-off NAND extraction desolders the NAND chips from the PCB for direct reading, but AES-256 encryption on many modern controllers means chip-off yields only ciphertext without the original controller to decrypt.

Why Chip-Off Fails After Block Erase

A NAND flash cell stores bits as trapped electrons on a floating gate isolated by two oxide layers. The number of electrons on that gate sets the cell's threshold voltage (Vt), which the sense amplifier measures to distinguish 0s from 1s. The physics of NAND cell programming and read is a charge-storage operation; cells retain their state because the oxide barrier traps the injected electrons.

The ERASE operation reverses this at the block level. The controller applies roughly 20V to the P-well substrate beneath every cell in the block and holds the control gates at ground. The resulting electric field pulls electrons off each floating gate through the tunnel oxide via Fowler-Nordheim tunneling. After ERASE, every cell in the block sits in the unprogrammed Vt distribution (near the erased state), read back as 0xFF. There is no residual charge pattern, no sub-threshold margin, no forensic technique available to a commercial lab that can recover the pre-erase program state. This is the mechanism that ends the recovery window. Before GC runs the ERASE, chip-off can read the raw programmed cells; after GC runs the ERASE, the chip holds no data to read.

SSD Garbage Collection Recovery FAQ

Can you recover data from an SSD after garbage collection?
If the SSD controller has physically erased the NAND blocks during garbage collection, those cells are reset to an unprogrammed state (0xFF) and no recovery method exists. If the drive lost power, firmware failed, or GC was interrupted before completing the erase cycle, the data may still reside on the raw NAND. PC-3000 SSD bypasses the controller's logical interface to read physical pages that the FTL marked as invalid. SATA SSD recovery starts at $200; NVMe starts at $200. Free evaluation, no data = no charge.
Why does my data recovery software show zeroes on my SSD?
Modern SSDs implement DZAT (Deterministic Read Zero After TRIM). When the OS deletes a file and sends a TRIM command, the controller immediately starts returning all zeroes for those logical addresses. This happens before garbage collection physically erases the NAND. Recovery software reads through the controller's logical interface, receives zeroes, and concludes the data is gone. The physical NAND cells may still hold the original charge states until GC erases them.
How long does garbage collection take to erase deleted SSD data?
GC timing varies by controller family. Samsung controllers (Elpis, Pascal, Phoenix) begin erasing TRIMmed blocks within seconds of idle time. Phison controllers batch GC operations and may take minutes. Silicon Motion controllers defer GC until the free block pool drops below a threshold, sometimes preserving stale pages for hours on lightly used drives. Powering off the SSD immediately after data loss is the only way to prevent GC from running.
What is the difference between TRIM and garbage collection?
TRIM is a command sent by the operating system to the SSD controller, marking specific logical block addresses as no longer in use. TRIM does not erase any NAND cells. Garbage collection is the controller's autonomous background process that reads valid pages out of dirty blocks, writes them to clean blocks, and physically erases the old blocks. TRIM tells the controller which data can go; garbage collection does the physical erasing.
What does DZAT mean for SSD data recovery?
DZAT stands for Deterministic Read Zero After TRIM. It is a SATA specification feature where the controller guarantees that any read to a TRIMmed logical block address returns all zeroes, regardless of whether the physical NAND still holds data. The NVMe equivalent is DLFEAT=001b (Deallocate Logical Block Features). DZAT blocks all software-based recovery because the controller intercepts read requests and returns zeroes before they reach the physical storage layer.
Should I power off my SSD immediately after losing data?
Yes. Garbage collection runs during idle time. Every second the SSD stays powered and idle gives the controller time to physically erase NAND blocks that TRIM marked as invalid. Powering off the drive freezes the state of the NAND. Do not reconnect the drive to a running operating system, do not run recovery software (it triggers controller activity), and do not attempt a format or partition repair. Ship the drive powered off to a lab with PC-3000 SSD capability. SATA SSD evaluation is free; recovery starts at $200.
Can PC-3000 SSD bypass DZAT and read the raw NAND?
PC-3000 SSD does not read data through the controller's standard SATA or NVMe interface, which is where DZAT enforcement happens. Instead, it forces the controller into a diagnostic state (Safe Mode or Techno Mode), uploads a custom loader into the controller's RAM, and reads raw physical NAND pages directly. In Techno Mode, garbage collection, wear leveling, and TRIM processing are all disabled. If the physical NAND cells have not yet been erased by GC, the data is accessible at the physical block address level.
Does over-provisioning affect how fast garbage collection erases data?
Yes. Over-provisioning (OP) is a reserve of NAND blocks hidden from the user and OS. A drive with 10% OP has a buffer of free blocks that the controller can write to while background GC cleans dirty blocks at its own pace. Higher OP means the controller can defer physical erasure longer. A nearly full SSD with minimal free space forces aggressive foreground GC, which erases TRIMmed blocks almost immediately to free space for incoming writes.
Does disabling TRIM prevent garbage collection?
No. TRIM is the command the OS uses to tell the controller which logical block addresses are no longer in use. Disabling TRIM (for example, running fsutil behavior set DisableDeleteNotify 1 on Windows, or on Linux both removing the discard mount option and disabling the periodic fstrim.timer systemd service) only stops the OS from notifying the drive about deletions. Garbage collection is an internal controller process governed by the drive's own firmware heuristics: free-block thresholds, wear-leveling counters, write-amplification targets, and idle-time detection. The controller still reclaims blocks by reading valid pages and erasing dirty ones; it simply has less information about which pages are actually invalid, which increases write amplification and can accelerate wear. Disabling TRIM may slightly delay the erasure of specific deleted files, but it does not stop the erase cycle itself.
What is the exact ATA command that sends a TRIM to an SSD?
TRIM is not a standalone ATA opcode. The host issues the DATA SET MANAGEMENT command (opcode 0x06, defined in ATA/ATAPI Command Set ACS-2 and later) with the Trim feature bit set in the Count register. The command payload is a list of LBA Range Entries. Each entry is an 8-byte structure: a 6-byte starting LBA followed by a 2-byte range length, packed into 512-byte sectors transmitted to the drive. The controller parses the ranges, walks the Flash Translation Layer, and marks every matching logical page as invalid in the FTL. No NAND cells are touched during this command; only the mapping table changes. The NVMe equivalent is the Dataset Management command with the Deallocate attribute, defined in NVM Express 2.0.
How does over-provisioning give data a longer life after TRIM?
Over-provisioning is NAND capacity the controller reserves for its own use: bad-block replacement, wear-leveling headroom, and write buffering. A 512GB consumer SSD with 7% OP has roughly 36GB of hidden reserve; a 512GB enterprise SSD with 28% OP has roughly 143GB. When the OS TRIMs a block, the data still occupies a physical page. The controller has no write pressure to erase that page until the OP pool gets depleted by new host writes. On a lightly used drive, a TRIMmed page can survive for many program/erase cycles across other blocks before wear-leveling schedules it for erase. This retention is measured in P/E cycles, not wall-clock time, which is why the PC-3000 SSD procedure is viable on drives that have been powered off quickly.
Why does chip-off recovery fail after garbage collection runs?
A NAND block erase is not a logical flag change; it is a physical reset of the memory cells. The controller applies roughly 20V to the block's substrate, which pulls electrons off each cell's floating gate through Fowler-Nordheim tunneling. After the ERASE operation, every cell in the block sits near the unprogrammed threshold voltage distribution, read by the sense amplifier as 0xFF. Desoldering the NAND and reading it on a chip-off reader does not bring those electrons back. The original charge states are gone at the physical layer, so no controller firmware, no PC-3000 SSD procedure, and no electron microscopy technique available in a commercial lab can reconstruct them.

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